Low-k isolation spacers for conductive regions

ABSTRACT

A multi-component low-k isolation spacer for a conductive region in a semiconductor structure is described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer adjacent to a sidewall of a gate electrode in a MOS-FET device.

BACKGROUND OF THE INVENTION

1) Field of the Invention

The invention is in the file of Semiconductor Structures.

2) Description of Related Art

For the past several years, the miniaturization and higher packing density of conductive regions in semiconductor structures, such as gate electrodes or metal interconnects, has been accompanied with an increase in fringe capacitance. Fringe capacitance, i.e. “cross-talk,” between such conductive regions may be detrimental to the performance of, for example, semiconductor devices or interconnect networks.

In order to overcome any dominant effects of fringe capacitance, higher power input may be provided to the semiconductor structure. However, this approach has drawbacks for today's low power requirements, e.g. extending battery life. Thus, a methods to isolate conductive regions in semiconductor structures is described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view representing a conductive region isolation by a pair of two-component low-k isolation spacers, in accordance with an embodiment of the present invention.

FIG. 2A-K illustrates cross-sectional views representing the formation of a planar MOS-FET with a gate electrode isolated by a pair of two-component low-k isolation spacers, in accordance with an embodiment of the present invention.

FIG. 3 illustrates a cross-sectional view representing a planar MOS-FET with a gate electrode isolated by a pair of two-component low-k isolation spacers, wherein the source/drain regions are faceted, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

A process for fabricating semiconductor structures and the resultant structures are described. In the following description, numerous specific details are set forth, such as specific dimensions and chemical regimes, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as patterning steps or wet chemical cleans, are not described in detail in order to not unnecessarily obscure the present invention. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

Disclosed herein is a multi-component (two or more components) low-k isolation spacer for isolating conductive regions in a semiconductor structure and a method to form a pair of two-component low-k isolation spacers for a gate electrode in a semiconductor device. Multi-component low-k isolation spacers comprised of higher-k upper portions robust to processing conditions and protected lower-k lower portions may enable a reduction in fringe capacitance and, hence, may enable low power operation of conductive regions. Thus, in accordance with an embodiment of the present invention, a multi-component spacer is used to isolate a conductive region in a semiconductor structure, enabling operation of the semiconductor structure with a reduced power consumption.

Isolation spacers may be used to physically separate neighboring conductive regions in a semiconductor structure, while protecting each of the conductive regions during various processing steps. A multi-component low-k isolation spacer may provide the same physical separation and protection of the conductive region as a conventional single-component isolation spacer, but may also enable a reduction in fringe capacitance, i.e. “cross-talk,” between conductive regions within a semiconductor structure. In accordance with an embodiment of the present invention, a multi-component low-k isolation spacer is formed directly adjacent to the sidewall of a conductive region. At least a portion of the multi-component isolation spacer is comprised of a low-k material and, therefore, fringe capacitance may be reduced significantly.

In addition to providing protection to and isolation for a conductive region, an isolation spacer should be sufficiently robust to withstand typical processing steps, such as ion bombardment implant steps, wet chemical cleans steps and dry etch steps (e.g. contact formation). Often, a higher-k material is required to provide such a robust isolation spacer, while a lower-k material is usually detrimentally impacted by such processing steps. Thus, in keeping with the requirement of robustness, in accordance with an embodiment of the present invention, at least a portion of the multi-component isolation spacer is comprised of a higher-k material, e.g. a material with a dielectric constant of at least 4.0. In a specific embodiment, the upper portion of the multi-component low-k isolation spacer is comprised of a higher-k material that provides durability and robustness to inhibit degradation of the multi-component low-k isolation spacer during processing steps. Meanwhile, the lower (protected) portion of the multi-component low-k isolation spacer is comprised of a lower-k material that enables a reduced fringe capacitance.

A replacement isolation spacer technique may be used to incorporate a multi-component low-k isolation spacer into a semiconductor structure with a conductive region. For example in accordance with an embodiment of the present invention, a replacement isolation spacer processing scheme is used to form a two-component isolation spacer wherein the top portion of the two-component isolation spacer is comprised of a higher-k material that provides durability and robustness, while the bottom portion is comprised of a lower-k material that enables a reduced fringe capacitance. Thus, the more fragile, lower-k portion is protected by the more robust higher-k portion.

In a metal-oxide-semiconductor field-effect transistor (MOS-FET), the incorporation of a raised source/drain region can increase the fringe capacitance between the raised source/drain region and a nearby gate electrode. Thus, in accordance with an embodiment of the present invention, a multi-component low-k isolation spacer is formed directly between a raised source/drain region and a gate electrode via a replacement isolation spacer processing scheme. The multi-component low-k isolation spacer physically separates (and hinders electrical shortage between) the raised source/drain region and the gate electrode, while mitigating fringe capacitance.

Multi-component low-k isolation spacers may be used to isolate any conductive region in a semiconductor structure. FIG. 1 illustrates a cross-sectional view representing a conductive region isolated by a pair of two-component low-k isolation spacers, in accordance with an embodiment of the present invention. A conductive region 102 sits above a structure 104 (e.g. a portion of a plurality of interconnects, a semiconductor substrate or an array of semiconductor or electronic devices) and is flanked by a pair of two-component isolation spacers 106, comprised of upper portions 106A and lower portions 106B. In one embodiment of the present invention, both upper portion 106A and lower portion 106B are directly adjacent to the same sidewall of conductive region 102, as depicted in FIG. 1. The widths of upper portion 106A and lower portion 106B need not be the same, however, upper portion 106A should be sufficiently wide as to protect the more fragile lower portion 106B during processing steps. In one embodiment, the width of upper portion 106A is the same as the width of lower portion 106B, as depicted in FIG. 1. In another embodiment, the width of upper portion 106A is greater than the width of lower portion 106B by at least 10 Angstroms. In an embodiment, the width of the top surface of lower portion 106B is in the range of 30-250 Angstroms and the width of bottom surface of upper portion 106B is in the range of 40-400 Angstroms. Lower portion 106B should be of a height sufficient to significantly reduce the fringe capacitance between conductive region 102 and another conductive region. In one embodiment, lower portion has a height of at least 50 Angstroms. Meanwhile, upper portion 106A should be of a height sufficient to protect lower portion 106A during processing steps. In an embodiment, upper portion has a height of at least 200 Angstroms.

Two-component isolation spacer 106, comprised of upper portion 106A and lower portion 106B, may be formed from any dielectric materials capable of suppressing a current flow. The dielectric constant of upper portion 106A should be different from the dielectric constant of lower portion 106B, otherwise a single-component isolation spacer would likely be sufficient. In fact, the dielectric constant of the more robust upper portion 106A should be greater that that of lower portion 106B. Otherwise, in accordance with an embodiment of the present invention, lower portion 106B would not provide the desired reduction in fringe capacitance. Thus, in accordance with an embodiment of the present invention, the dielectric constant of upper portion 106A is greater than the dielectric constant of lower portion 106B. In one embodiment, the dielectric constant of lower portion 106B is in the range of 2.0-4.0 and the dielectric constant of upper portion 106A is in the range of 4.0-7.5. In another embodiment, the dielectric constant of upper portion 106A is at least twice the dielectric constant of lower portion 106B. In an embodiment, lower portion 106B is comprised of silicon dioxide and upper portion 106A is comprised of a material selected from the group consisting of silicon nitride, silicon oxy-nitride and carbon-doped silicon nitride. In one embodiment, the dielectric constant of lower portion 106B is in the range of 2.5-3.5. In an embodiment, lower portion 106B is comprised of a material selected from the group consisting of a porous film or a fluorinated oxide.

Conductive region 102 may be any conductive region in a semiconductor structure. For example, in accordance with an embodiment of the present invention, conductive region 102 is a gate electrode in a MOS-FET device. Thus, in one embodiment, structure 104 is a semiconductor substrate comprising a channel region. In an embodiment, conductive region 102 is a gate electrode comprised of doped polycrystalline silicon or a silicide thereof. In another embodiment, conductive region 102 is a gate electrode comprised of a metal layer such as but not limited to metal nitrides, metal carbides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides, e.g. ruthenium oxide. When conductive region 102 is a gate electrode, it may further comprise a gate dielectric layer between the gate electrode and structure 104. In one embodiment, the gate dielectric layer is formed by a thermal oxidation process and is comprised of silicon dioxide or silicon oxy-nitride. In another embodiment, the gate dielectric layer is formed by chemical vapor deposition or atomic layer deposition and is comprised of a high-k dielectric layer such as, but not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride or lanthanum oxide.

In accordance with an alternative embodiment of the present invention, conductive region 102 is an interconnect from a plurality of interconnects that connect various electronic and semiconductor devices into a global circuitry. Thus, structure 104 may comprise a portion of a plurality of interconnects or an array of semiconductor or electronic devices. In one embodiment, structure 104 is a layer of metal interconnects. In another embodiment, structure 104 is an array of complimentary metal-oxide-semiconductor (CMOS) transistors incased in a dielectric layer. The interconnect 102 may comprise any suitable material that can conduct a current. In one embodiment, the interconnect is comprised of copper, silver, aluminum or an alloy thereof. In another embodiment, the interconnect comprises an array of interspersed carbon nanotubes. The interconnect may comprise a barrier layer, which may comprise any material suitable to inhibit electro-migration within a plurality of interconnects, to prevent oxidation of the interconnect or to provide a surface for nucleation in a damascene process. In one embodiment, the barrier layer is comprised of tantalum, titanium, tantalum nitride, titanium nitride or a combination thereof. The interconnect may also comprise a capping layer. In an embodiment, the capping layer comprises iridium, ruthenium, cobalt, cobalt/tungsten alloy, cobalt/tungsten phosphide, cobalt boron phosphide or a combination thereof.

A replacement isolation spacer technique may be used to incorporate a multi-component low-k isolation spacer into a semiconductor structure with a conductive region, e.g. a gate electrode. FIGS. 2A-K illustrate cross-sectional views representing the formation of a planar MOS-FET with a gate electrode isolated by a pair of two-component low-k isolation spacers, in accordance with an embodiment of the present invention.

Referring to FIG. 2A, a gate electrode 202 may be formed above a substrate 204. Substrate 204 may be non-insulating and may comprise a semiconducting material or epitaxial layer. In one embodiment, substrate 204 is formed by doping a crystalline silicon, germanium or silicon/germanium layer with an appropriate charge carrier, such as but not limited to phosphorus, arsenic, boron, indium or a combination thereof. In another embodiment, substrate 204 is comprised of a III-V material such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide or indium antimonide. In one embodiment, substrate 204 is comprised of an epitaxial layer grown atop a distinct crystalline substrate. In accordance with another embodiment of the present invention, substrate 204 comprises an insulating layer. In one embodiment, the insulating layer is comprised of silicon dioxide, silicon nitride, silicon oxy-nitride or a high-k dielectric layer. In an embodiment, substrate 204 is comprised of an epitaxial layer and a bulk crystal substrate with an insulating layer between the bulk crystal substrate and the epitaxial layer forming, for example, a silicon-on-insulator substrate.

A gate dielectric layer 208 may be formed between substrate 204 and gate electrode 202, as depicted in FIG. 2A. In one embodiment, gate dielectric layer 208 is formed by a thermal oxidation process and is comprised of silicon dioxide or silicon oxy-nitride. In another embodiment, gate dielectric layer 208 is formed by chemical vapor deposition or atomic layer deposition and is comprised of a high-k dielectric layer such as, but not limited to, hafnium oxide, zirconium oxide, hafnium silicate, hafnium oxy-nitride or lanthanum oxide.

Gate electrode 202 may comprise any conductive material and may be formed by a subtractive etching process scheme or by a replacement gate process scheme. In one embodiment, gate electrode 202 is comprised of a polycrystalline silicon gate electrode, wherein the charge-carrier dopant impurities are implanted during fabrication of the tip and source/drain regions, described below. In another embodiment, gate electrode 202 is comprised of a metal layer such as but not limited to metal nitrides, metal carbides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides, e.g. ruthenium oxide. In one embodiment, a protective layer 220 is retained above gate electrode 202, as depicted in FIG. 2A.

A tip extension 210 may be formed by implanting charge-carrier dopant impurity atoms into 204. Gate electrode 202 may act to mask a portion of substrate 204 to form self-aligned tip extensions 210 and to define a channel region 212. In one embodiment, substrate 204 is comprised of crystalline silicon, germanium or silicon/germanium and the charge-carrier dopant impurity atoms used to form tip extension 210 are selected from the group consisting of boron, arsenic, indium or phosphorus. In another embodiment, substrate 204 is comprised of a III-V material such as but not limited to gallium nitride, gallium phosphide, gallium arsenide, indium phosphide or indium antimonide and the charge-carrier dopant impurity atoms used to form tip extension 210 are selected from the group consisting of carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

In accordance with an embodiment of the present invention, a sacrificial gate isolation spacer is used as a placeholder for the subsequent formation of a multi-component low-k isolation spacer. The sacrificial gate isolation spacer should be sufficiently robust to withstand processing steps (e.g. dry etch patterning, wet chemical cleans and ion bombardment implant) that occur prior to its removal, but should also be sufficiently easy to remove when no longer required. Thus, a sacrificial gate isolation spacer may be formed by any suitable technique that provides a robust dielectric layer directly adjacent to the sidewalls of gate electrode 202. In accordance with an embodiment of the present invention, referring to FIG. 2B, a material layer 230 is deposited by a chemical vapor deposition process and is conformal with the structure formed in FIG. 2A. In one embodiment, material layer 230 is comprised of an insulating layer. In a particular embodiment, material layer 230 is comprised of silicon dioxide, silicon oxy-nitride, carbon-doped silicon oxide, a low-temperature furnace oxide or a combination thereof. In another embodiment, material layer 230 is comprised of silicon nitride or carbon-doped silicon nitride. Material layer 230 may be deposited to a thickness selected to determine the final width of the sacrificial gate isolation spacer. In one embodiment, material layer 230 is deposited to a thickness in the range of 30-250 Angstroms.

Referring to FIG. 2C, sacrificial isolation spacer 235 is formed from material layer 230 by, for example, an anisotropic etch process. In one embodiment, material layer 230 is dry etched by a remote plasma etch or a reactive ion etch process. In another embodiment, material layer 230 is patterned to form sacrificial isolation spacer 235 by using a vertical dry or plasma etch process comprising fluorocarbons of the general formula C_(x)F_(y), where x and y are natural numbers. In another embodiment, material layer 230 is patterned to form sacrificial isolation spacer 235 by using a vertical dry or plasma etch process comprising free radical fluorocarbons. Sacrificial isolation spacer 235 may sit above the top surface of substrate 204 and may have a width substantially equal to the original thickness of material layer 230, i.e. 30 Angstroms to 250 Angstroms. In accordance with an embodiment of the present invention, sacrificial isolation spacer 235 resides above tip extensions 210. In one embodiment, sacrificial isolation spacer 235 forms a hermetic seal with gate electrode 202 and the top surface of substrate 204 to encapsulate gate dielectric layer 208, as depicted in FIG. 2C. In one embodiment, a wet chemical cleaning process step comprising the application of an aqueous solution of hydrofluoric acid, ammonium fluoride or both follows the formation of sacrificial isolation spacer 235.

Referring to FIG. 2D, source/drain regions 214 may subsequently be formed by implanting charge carrier dopant impurity atoms into substrate 204. Sacrificial gate isolation spacers 235 and gate electrode 202 may act to mask a portion of substrate 204 to provide self-aligned source/drain regions 214. In effect, the width of sacrificial gate isolation spacer 235 may play a role in determining the dimensions and location of source/drain regions 214. In one embodiment, boron, arsenic, phosphorus, indium or a combination thereof is implanted into substrate 204 to form source/drain regions 214. In another embodiment, the charge-carrier dopant impurity atoms used to form source/drain region 214 are selected from the group consisting of carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

Referring to FIG. 2E, portions of substrate 204, including source/drain region 214, may be removed to form etched-out region 216 in substrate 204. Etched-out region 216 may be formed by any suitable technique that selectively removes a portion of crystalline substrate 204 without significantly impacting gate dielectric layer 208, gate electrode 202 or tip extension 210, such as a dry etch or a wet etch process. In one embodiment, etched-out region 216 is formed by a dry plasma etch using NF₃, HBr, SF₆/Cl or Cl₂ or a wet etch using NH₄OH or tetramethylammonium hydroxide. In one embodiment, protective layer 220 protects gate electrode 202 during the formation of etched-out region 216. In another embodiment, etched-out region 216 is formed to a depth sufficient to remove the charge-carrier dopant impurities implanted to form source/drain region 214, as depicted in FIG. 2E.

Referring to FIG. 2F, epitaxial source/drain region 218 may be formed selectively in etched-out region 216 from FIG. 2E. In accordance with an embodiment of the present invention, epitaxial source/drain region 218 is a strain-inducing semiconductor region that imparts a compressive uniaxial strain to substrate 204 and, hence, to channel region 212. In another embodiment, epitaxial source/drain region 218 is a strain-inducing semiconductor region that imparts a tensile uniaxial strain to substrate 204 and, hence, to channel region 212. In one embodiment, substrate 204 is comprised of Si_(x)Ge_(1-x) where 0≦x≦1 and epitaxial source/drain region 218 is comprised of Si_(y)Ge_(1-y) where 0≦y≦1 and y≠x. In another embodiment, substrate 204 is comprised of silicon and epitaxial source/drain region 218 is comprised of carbon-doped silicon. In an embodiment, the top surface of epitaxial source/drain region 218 is raised above the top surface of crystalline substrate 204, as depicted in FIG. 2F.

In accordance with an embodiment of the present invention, charge-carrier dopant impurity atoms are implanted into epitaxial source/drain region 218 either during (i.e. in situ) or subsequent to the formation of epitaxial source/drain region 218. In one embodiment, epitaxial source/drain region 218 is comprised of Si_(x)Ge_(1-x) where 0≦x≦1 or carbon-doped silicon and the charge-carrier dopant impurity atoms implanted are selected from the group consisting of boron, arsenic, indium or phosphorus. In another embodiment, epitaxial source/drain region 218 is comprised of a III-V material and the charge-carrier dopant impurity atoms implanted are selected from the group consisting of carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

Referring to FIG. 2G, sacrificial isolation spacers 235 may be removed by any suitable technique that does not significantly impact substrate 204, including tip extensions 210 and epitaxial source/drain regions 218, gate dielectric layer 208 or gate electrode 202. In accordance with an embodiment of the present invention, sacrificial isolation spacers 235 are removed by a dry etch or wet etch process. In one embodiment, sacrificial isolation spacers 235 are comprised of silicon dioxide, silicon oxy-nitride, carbon-doped silicon oxide or a low-temperature furnace oxide and are removed with a wet etch comprising aqueous hydrofluoric acid, ammonium fluoride or both. In another embodiment, sacrificial isolation spacers 235 are comprised of silicon nitride or carbon-doped silicon nitride and are removed with a wet etch comprising aqueous phosphoric acid. In accordance with an embodiment of the present invention, upon removal of sacrificial isolation spacer 235, a trench 240 is formed directly between epitaxial source/drain region 218 and gate electrode 202, as depicted in FIG. 2G. In one embodiment, trench 240 has a height in the range of 50-1000 Angstroms.

The structure from FIG. 2G provides a framework for a replacement isolation spacer. In accordance with an embodiment of the present invention, referring to FIG. 2H, a material layer 250 is deposited by a chemical vapor deposition process and is conformal with the structure formed in FIG. 2G. Material layer 250 will ultimately be used to form the lower portion of a multi-component isolation spacer and is therefore comprised of a material that could be detrimentally impacted during typical processing steps (such as ion bombardment implant steps, wet chemical cleans steps and dry etch steps). In one embodiment, material layer 250 is comprised of an insulating layer. In a particular embodiment, material layer 250 is comprised of silicon dioxide, a porous film or a fluorinated oxide. In another embodiment, material layer has a dielectric constant in the range of 2.0-4.0. In one embodiment, material layer has a dielectric constant in the range of 2.5-3.5. Material layer 250 may be deposited to a thickness sufficient to fill trench 240. In an embodiment, material layer 250 is deposited to a thickness in the range of 30-250 Angstroms.

Referring to FIG. 2I, all portions of material layer 250 that are not in trench 240 may be removed to provide lower portions 255 of a replacement low-k isolation spacer. In accordance with an embodiment of the present invention, lower portions 255 are flush with the top surface of epitaxial source/drain regions 218, as depicted in FIG. 2I. In one embodiment, a wet etch process step comprising the application of an aqueous solution of hydrofluoric acid, ammonium fluoride or both may be used to remove those portions of material layer 250 that are not in trench 240.

Upper portions of a replacement low-k isolation spacer may then be formed by any suitable technique that provides a dielectric layer directly adjacent to the sidewalls of gate electrode 202 and above lower portions 255. In accordance with an embodiment of the present invention, referring to FIG. 2J, a material layer 260 is deposited by a chemical vapor deposition process and is conformal with the structure formed in FIG. 2I. In one embodiment, material layer 260 is comprised of an insulating layer. In a particular embodiment, material layer 260 is comprised of silicon dioxide, silicon oxy-nitride, carbon-doped silicon oxide, silicon nitride, carbon-doped silicon nitride or a combination thereof. In another embodiment, material layer 260 has a dielectric constant in the range of 4.0-7.5. In an embodiment, material layer 260 has a dielectric constant at least twice the dielectric constant of lower portion 255. Material layer 260 may be deposited to a thickness selected to determine the final width of the upper portion of a replacement low-k isolation spacer. In one embodiment, material layer 260 is deposited to a thickness in the range of 40-400 Angstroms.

Referring to FIG. 2K, upper portions 265 of a replacement low-k isolation spacer 270 are formed from material layer 260 by, for example, an anisotropic etch process. In one embodiment, material layer 260 is dry etched by a remote plasma etch or a reactive ion etch process. In another embodiment, material layer 260 is patterned to form upper portions 265 by using a vertical dry or plasma etch process comprising fluorocarbons of the general formula C_(x)F_(y), where x and y are natural numbers. In another embodiment, material layer 260 is patterned to form upper portions 265 by using a vertical dry or plasma etch process comprising free radical fluorocarbons. In accordance with an embodiment of the present invention, upper portions 265 have a slower etch rate than, i.e. are more robust than and hence protect, lower portions 255. Upper portion 265 sit directly above the top surface of lower portion 255 of replacement low-k isolation spacer 270 and may have a width at the top surface of lower portion 255 substantially equal to the original thickness of material layer 260. In accordance with an embodiment of the present invention, upper portions 265 of replacement low-k isolation spacer are wider than lower portions 255, as depicted in FIG. 2K. In one embodiment, upper portion 265 is at least 10 Angstroms wider than lower portion 255. In another embodiment, the width of upper portion 265 at the top surface of lower portion 255 is in the range of 40-400 Angstroms. In an embodiment, upper portion 265 directly overlaps source/drain region 218, as depicted in FIG. 2K. In one embodiment, upper portion 265 directly overlaps source/drain region 218 by at least 10 Angstroms. In an embodiment, a wet chemical cleaning process step comprising the application of an aqueous solution of hydrofluoric acid, ammonium fluoride or both follows the formation of upper portions 265.

Thus, referring to FIG. 2K, a planar MOS-FET 200 comprising a multi-component low-k isolation spacer may be formed via a replacement isolation spacer process. Planar MOS-FET 200 may be an N-type or a P-type semiconductor device and may be incorporated into an integrated circuit by conventional process steps, as known in the art. As will be appreciated in the typical integrated circuit, both N- and P-channel transistors may be fabricated in a single substrate or epitaxial layer to form a CMOS integrated circuit.

As depicted in FIGS. 2A-K, epitaxial source/drain region 218 may have a facet-less sidewall and may thus be flush with sacrificial isolation spacer 235. In accordance with an embodiment of the present invention, lower portion 255 has a top surface width substantially equal to the width of sacrificial isolation spacer 235. In one embodiment, the top surface width of lower portion 255 is in the range of 30-250 Angstroms. Alternatively, the epitaxial source/drain region may comprise a faceted sidewall. Referring to FIG. 3, epitaxial source/drain region 318 has a faceted sidewall 380. In accordance with an embodiment of the present invention, lower portion 355 has a width greater than the width of the sacrificial isolation spacer. In one embodiment, the top surface width of lower portion 355 is in the range of 75-250 Angstroms. In an embodiment, upper portion 365 directly overlaps source/drain region 318, as depicted in FIG. 3. In one embodiment, upper portion 365 directly overlaps source/drain region 318 by at least 10 Angstroms.

The present invention is not limited to the formation of planar MOS-FETs comprising multi-component low-k isolation spacers. For example, in accordance with an embodiment of the present invention, a bipolar transistor, a memory transistor or a micro-electronic machine (MEM) comprising multi-component low-k isolation spacers is formed. Also, in accordance with another embodiment of the present invention, devices with a three-dimensional architecture, such as independently accessed double gate devices, FIN-FETs, tri-gate devices and gate-all-around devices, are formed incorporating multi-component low-k isolation spacers.

Therefore, a multi-component low-k isolation spacer and its method of formation for use with a conductive region in a semiconductor structure has been described. In one embodiment, a replacement isolation spacer process is utilized to enable the formation of a two-component low-k isolation spacer directly adjacent to the sidewall of a conductive region in a semiconductor device. 

1. A method of making a semiconductor structure comprising: forming a gate electrode above the top surface of a substrate, said gate electrode having a sidewall; forming a source/drain region adjacent to, but separated by a trench from, said gate electrode, said source/drain region having a sidewall and having a top surface above the top surface of said substrate; forming, in said trench and directly adjacent to said sidewall of said gate electrode and directly adjacent to said sidewall of said source/drain region, a first portion of a multi-component dielectric spacer, said first portion having a height less than the height of said sidewall of said gate electrode; and forming a second portion of said multi-component dielectric spacer, said second portion disposed directly above said first portion and directly adjacent to said sidewall of said gate electrode, wherein the dielectric constant of said first portion is lower than the dielectric constant of said second portion.
 2. The method of claim 1 wherein the dielectric constant of said second portion is at least twice the dielectric constant of said first portion.
 3. The method of claim 1 wherein the dielectric constant of said first portion is in the range of 2.0-4.0, and wherein the dielectric constant of said second portion is in the range of 4.0-7.5.
 4. The method of claim 3 wherein said first portion is comprised of a material selected from the group consisting of silicon dioxide, a porous film and a fluorinated oxide, and wherein said second portion is comprised of a material selected from the group consisting of silicon nitride, silicon oxy-nitride and carbon-doped silicon nitride.
 5. The method of claim 1 wherein the width of the top surface of said first portion is in the range of 30-250 Angstroms.
 6. A method for making a semiconductor device comprising: forming a substrate; forming a gate dielectric layer, wherein said gate dielectric layer is above said substrate; forming a gate electrode, wherein said gate electrode is above said gate dielectric layer; forming a first gate isolation spacer, wherein said first gate isolation spacer is directly adjacent to a sidewall of said gate electrode; removing a portion of said substrate to form an etched-out region; forming a source/drain region above said etched-out region, wherein the top surface of said source/drain region is above the top surface of said substrate, and wherein a sidewall of said source/drain region is directly adjacent to said first gate isolation spacer; removing said first gate isolation spacer to provide a trench between said sidewall of said source/drain region and said sidewall of said gate electrode; forming a first dielectric material layer above said source/drain region, directly adjacent to said sidewall of said gate electrode, above said gate electrode and in said trench; removing the portion of said first dielectric material layer that is not in said trench to provide a first portion of a second gate isolation spacer, wherein said first portion of said second gate isolation spacer is above said substrate and directly in between said sidewall of said gate electrode and said sidewall of said source/drain region; forming a second dielectric material layer above said source/drain region, directly adjacent to said sidewall of said gate electrode, above said gate electrode and directly above said first portion of said second gate isolation spacer; and etching said second dielectric material layer to provide a second portion of said second gate isolation spacer, wherein said second portion of said second gate isolation spacer is directly above said first portion of said second gate isolation spacer and is directly adjacent to said sidewall of said gate electrode.
 7. The method of claim 6 wherein the dielectric constant of said second portion of said second gate isolation spacer is at least twice the dielectric constant of said first portion of said second gate isolation spacer.
 8. The method of claim 6 wherein the dielectric constant of said first portion of said second gate isolation spacer is in the range of 2.0-4.0, and wherein the dielectric constant of said second portion of said second gate isolation spacer is in the range of 4.0-7.5.
 9. The method of claim 8 wherein said first portion of said second gate isolation spacer is comprised of a material selected from the group consisting of silicon dioxide, a porous film and a fluorinated oxide, and wherein said second portion of said second gate isolation spacer is comprised of a material selected from the group consisting of silicon nitride, silicon oxy-nitride and carbon-doped silicon nitride.
 10. The method of claim 6 wherein the width of said second portion of said second gate isolation spacer is greater than the width of said first portion of said second gate isolation spacer.
 11. The method of claim 10 wherein the width of the top surface of said first portion of said second gate isolation spacer is in the range of 30-250 Angstroms.
 12. The method of claim 6 wherein said first gate isolation spacer is comprised of a low-temperature furnace oxide.
 13. The method of claim 6 wherein said sidewall of said source/drain region is facet-less.
 14. The method of claim 13 wherein said trench has a height in the range of 50-1000 Angstroms.
 15. The method of claim 6 wherein said sidewall of said source/drain region is faceted.
 16. The method of claim 6 wherein the top surface of said first portion of said second gate isolation spacer is flush with the top surface of said source/drain region.
 17. The method of claim 6 wherein said first portion of said second gate isolation spacer has a faster etch rate than said second portion of said second gate isolation spacer. 